Intel Fights Order Cycle Time Variance
Intel, the world’s largest maker of computer chips, was facing challenges with both the length and variability of order cycle times – from the time the order was dropped to the warehouse until the time it was shipped. This added to overall complexity, made order promising to customers difficult, and increased the time of the promised ship date to customers.
Edwards’ Intel colleague Grant Lindsey decided to use a Theory of Constraints approach to attack the problem.
“We’ve learned that proven, robust solutions for manufacturing like TOC can be applied to warehousing, and that as a result very rapid results can be achieved,” Edwards said.
The TOC-based analysis identified that one step in the process – the packing operation – was the overall system constraint. Order picking and consolidation steps before the packing operation, and shipment preparation after packing, could all operate at much higher rates per hour. This meant that the fulfillment system as a whole could only process as many orders per hour as the packing station no matter how many orders could be picked before packing or processed on the back end.
This situation also resulted in picked orders being staged ahead of the packing operating at levels that created complexity and variability - too much “buffer” inventory. This complexity also meant that frequently the constrained packing area operated at lower than its maximum capacity, further limiting total throughout.
Typically, to improve total output/throughput, a company using TOC would seek to improve the processing capability of the constraint (which, as in The Goal, often then causes another process to become the constraint). But in Intel’s case, that was not really possible. Physical limitations in the distribution area, and no budget to add any sort of automation, meant the packing process throughput would have to stay static for now.
Given this, Intel applied the Drum-Buffer-Rope concept that is a key tenet of TOC to its distribution processes. That concept first identifies the constraint – the drum – that in reality sets the cadence for the entire process.
In Intel’s case, that again was the packing step. The buffer is the “work-in-process” before the constraint. The constraint has to be fed consistently – if it isn’t, and the constrained process can’t reach its limit, then total system throughput will be lower.
But you don’t want too much buffer inventory – that can clog up the operation, and actually again reduce the output of the constrained process. That, in fact, is exactly what was happening at Intel.
So, said Edwards, you need to monitor the process and send feedback upstream – the rope – to pull enough work-in-process (in Intel’s case picked and staged bulk product) to keep the constrained packing operation fully utilized, but not awash in product.
Edwards said Intel used several tools to send the demand signals, including low tech but effective tools such as walkie-talkies, as well as electronic signals based on scanning activity by pickers with Radio Frequency devices. (See figure nearby.)
Flow, not Utilization
Edwards noted that nearly all distribution centers focus heavily on worker utilization – keeping associates fully busy and minimizing “indirect time” (work not directly associated with processing goods or orders).
He suggested that many operations would benefit from a stronger focus on product flow – even at the “cost” of sometimes letting workers in certain areas be idle for periods of time.
“We were rewarding and incenting our pickers for their output, even though the downstream packing process couldn’t handle that volume,” Edwards said. As a result, inventory piled up.
When the new process was implemented, results were seen almost immediately, and eventually delivered substantial improvements in many areas across eight Intel DCs:
- Average order cycle times decreased by 75%
- Variability in cycle times decreased at a similar level
- Total throughput actually increased somewhat, as the constrained packing area was more fully utilized by better buffer management
These improvements were achieved with no investment other than travel costs to facilities.
At the beginning, Intel used a three-hour buffer before the packing stations, but over time was able to reduce it to just a one hour planned buffer. A planned buffer under one hour sometimes led to the packing stations not having work.
Full DC View Lowers Inventory Levels by a Full Day
The initial project focused on reducing cycle times and variability with orders after they had been dropped to the warehouse. After that success, the Intel logistics team looked at the full order cycle time using TOC, from the time the orders were created in the ERP system.
Like many companies, Intel’s system “locked” inventory when an order had available inventory and a known ship date. A few days before the ship date, the order was dropped to the warehouse.
Again using TOC principles, it was determined Intel should decouple this process, and not tie up the inventory so far in advance. Changing the process led to a reduction in the inventory needed to support distribution from 2.5 days previously to 1.5 days after the improvement – a hard savings of at least $15 million in inventory carrying costs.
The key lessons learned, according to Edwards: first, that Theory of Constraints really has a place in improving logistics and distribution processes. Second, that “you can decrease inventory levels and responsiveness by tackling cycle time.”
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